The increasing requirement for high-density mounting in semiconductor packages in recent years has been causing a shift from chip on board (COB) mounting that uses wire bonding technique to flip-chip mounting that uses face-down bonding technique.
Semiconductor chips which are mounted on a circuit board by the flip-chip mounting include one that comprises a semiconductor substrate, electrodes, a passivation layer, a barrier metal layer and solder bump. The electrodes are disposed on the semiconductor substrate. The passivation layer is disposed on the electrodes and has an opening that penetrates therethrough in the thickness direction. The barrier metal layer is located on the electrodes below the opening of the passivation layer, and contains phosphorous (P). The solder bump is formed on the barrier metal layer.
The barrier metal layer of a semiconductor chip that is constituted as described above usually has a phosphorus-rich portion in the surface region on the solder bump side thereof. The phosphorus-rich portion is a region that has a relatively higher phosphorus content. The mechanical strength of the phosphorus-rich portion is lower than that of the other region. This means that an increase in the thickness of the phosphorus-rich portion in the barrier metal layer results in a decrease in mechanical strength of the junction between the solder bump and the barrier metal layer. Thus when thermal stress repetitively acts on the circuit board whereon a semiconductor chip is mounted, for example, there have been such cases as cracks are generated in the junction, and the solder bump eventually peels off. A technology to suppress the thickness of the phosphorus-rich portion as a whole for the purpose of solving this problem is disclosed in Patent Document 1.
Specifically, according to Patent Document 1, a semiconductor chip is manufactured as follows. First, electrode pads are formed on a semiconductor substrate. The electrode pad is formed from an electrically conductive material such as aluminum. Then a passivation film is formed so as to cover a portion that is not covered with the electrode pad in the electrode-pad-forming surface of the semiconductor substrate and also cover a portion surrounding the electrode pad. Then electroless nickel plating is applied to form a nickel layer at a portion that is not covered with the passivation film on the electrode pad, followed by electroless gold plating to form a gold layer on the nickel layer. Then a solder is placed on the gold layer and is heated so as to form solder bump, thereby manufacturing the semiconductor chip having the bump. The nickel layer and the gold layer function as barrier metal layers that provide the base for the solder bump.
Manufacturing the semiconductor chip by the method described in Patent Document 1 makes it possible to suppress the diffusion of nickel that constitutes the nickel layer into the solder bump by means of the gold layer when forming the solder bump. This enables it to improve the reliability by suppressing the formation of a thick intermetallic compound layer, which is relatively brittle, at the interface between nickel and the solder.
Patent Document 1: Japanese Unexamined Patent Publication (Kokai) No. 2004-273959